The present invention generally relates to the field integrated circuits, and particularly to a scale-invariant topology and traffic allocation in multi-node system-on-chip switching fabrics.
Integrated circuit design and implementation is becoming more and more complex as the functionality and size of the circuits increase. A variety of users and manufacturers of devices utilizing integrated circuits desire an increasing array of functionality and performance in lower cost devices. Therefore, to comply with this mandate, producers of integrated circuit must become more efficient in the design and optimization of the circuits to ensure competitive positioning of their products.
One such area for optimization includes organization and routing of the components of the integrated circuit. As the number of components increase, the complexity of routing between the functional blocks even further increases.
For example, high complexity semiconductor devices, such as system-on-chip devices and the like, may be organized as networks or interconnected patterns of functional blocks. An important issue in the design of such complex system-on-chip integrated circuits is the optimal allocation of path attributes among the elements making up the fabric. However, because of the vast complexity of these devices due to the number of components, designs may be realized to provide desired functionality but may not be the most optimal solution.
Therefore, it would be desirable to provide a system and method for a scale-invariant topology and traffic allocation in multi-node system-on-chip switching fabrics.
Accordingly, the present invention is directed to a scale-invariant topology and traffic allocation in multi-node system-on-chip switching fabrics. In a first aspect of the present invention, a method for allocating resources in a design of an integrated circuit includes receiving resource data for components of an integrated circuit. The resource data is suitable for indicating consumption by the components of at least one resource. Integrated circuit resources for the components of the integrated circuit are allocated according to a power law distribution as applied to the received resource data.
In an additional aspect of the present invention, a method for allocating resources in a design of an integrated circuit includes receiving resource data for components of an integrated circuit. The resource data is suitable for indicating consumption by the components of at least one resource. Integrated circuit resources for the components of the integrated circuit are allocated according to a power law distribution as applied to the received resource data. The allocation of integrated circuit resources is optimized by utilizing a genetic algorithm.
In a further aspect of the present invention, a system for allocating resources in a design of an integrated circuit includes a memory suitable for storing a program of instructions and a processor suitable for performing a program of instructions. The program of instructions configures the processor to receive resource data for components of an integrated circuit. The resource data is suitable for indicating consumption by the components of at least one resource. Integrated circuit resources for the components of the integrated circuit are allocated according to a power law distribution as applied to the received resource data.
It is to be understood that both the forgoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the invention as claimed. The accompanying drawings, which are incorporated in and constitute a part of the specification, illustrate an embodiment of the invention and together with the general description, serve to explain the principles of the invention.